1. Field of the Invention
The present invention relates to split-gate memory cells of the type utilizable in an erasable programmable read only memory (EPROM) and, more particularly, to a split-gate memory cell that utilizes a polysilicon spacer to define the gate length of the series select transistor in a virtual-ground split-gate EPROM cell. Since the length of the polysilicon spacer can be controlled with great precision, misalignment problems associated with prior art split-gate cells are eliminated, thereby reducing cell size.
2. Discussion of the Prior Art
Virtual-ground split-gate EPROM cells have been proposed as a means for improving on the packing density and yield of conventional "T" EPROM cells. These cells offer two key features. First, the use of buried N+ bits lines drastically reduces the number of contacts needed in the memory array. This confers an immediate yield advantage, since metal coverage of contact topology is a significant cause of yield loss in scaled integrated circuit technologies. By sharing bit line contacts among a large number of cells, the layout area associated with each cell is further reduced. Second, providing a series select transistor associated with each floating gate insures that the cell cannot be inadvertently turned on due to voltage coupled from the drain to the floating gate. This significantly relieves the constraints on drain programming voltage experienced with a convention T-cell EPROM. Furthermore, associating a series select transistor with each floating-gate confers asymmetry to the operation of the cell. If the source and drain terminals of the cell are interchanged, no programming can take place. This considerably simplifies the programming decoding of the array, since the cell next to the one being programmed is inherently resistant to programming: it cannot be disturbed by the high voltage applied to its source node, which also serves as the drain node of the programmed cell.
U.S. Pat. No. 4,639,893 issued Jan. 27, 1987 to Boaz Eitan discloses an implementation of a virtual-ground split-gate EPROM cell. A second split-gate cell implementation has been reported by Ali et al., "A new Staggered Virtual-Ground array architecture implemented in a 4Mb CMOS EPROM", 1989 VLSI Circuits Conference, Tokyo, Japan.
These two implementations of a split-gate cell have the same cross-section, which is shown in FIG. 1A. The cells differ only in the way in which they are arrayed. The Eitan array is illustrated in FIG. 1B. The Ali et al array is illustrated in FIG. 1C.
Both of these cells suffer from the same major problem. That is, the length of the series select transistor is defined by the masking of the buried N+ layer. This creates several problems. First, the length of the series select transistor and, hence, the electrical characteristics of the cell, are dependent upon the alignment of the buried N+ region to the polysilicon floating gate. This introduces significant variation in cell performance from die to die and from wafer to wafer. Second, the uncertainty in the final position of the buried N+ region causes variation in the series resistance of the buried bit line, causing further variation in cell performance. Third, in order to insure that the resistance of the buried N+ bit line is acceptably low, under worst-case misalignment of the buried N+ region, the width of the buried N+ bit line must be drawn wider than the required minimum. This increases the overall area of the cell.